Rigorous Design of FDIR Systems with BIP (InterAVT 2019 - Interactive Workshop on the Industrial Application of Verification and Testing) - ETAPS 2019

Sat 6 - Thu 11 April 2019 Prague, Czech Republic

Who

Iulia Dragomir, Saddek Bensalem

Track

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When

Sat 6 Apr 2019 10:20 - 10:30 at S6 - I

Iulia Dragomir

Saddek Bensalem

Verimag

Time Zone

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Session Program

Sat 6 Apr
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	09:00 - 10:30	IInterAVT at S6

	09:00 30m Talk		Welcome to InterAVT 2019 InterAVT Stylianos Basagiannis United Technologies Research centre, Goetz Botterweck Lero - The Irish Software Research Centre and University of Limerick, Anila Mjeda Lero - The Irish Software Research Centre and University of Limerick
	09:30 30m Talk		Invited Talk - "End-to-End Verification of Intelligent Cyber-Physical Systems: Progress and Challenges" InterAVT Nathan Fulton MIT-IBM Watson AI Lab
	10:00 10m Talk		Cross Programming Language Taint Analysis for the IoT Ecosystem InterAVT Pietro Ferrara JuliaSoft SRL, Italy, Amit Kr Mandal Università Ca' Foscari, Venezia, Italy, Agostino Cortesi Università Ca' Foscari Venezia, Fausto Spoto U. Verona
	10:10 10m Talk		FVL: Formal Verification in the Loop to Enhance Verification of Safety-Critical Cyber-Physical Systems InterAVT Cinzia Bernardeshi Univ. of Pisa, Andrea Domenici University of Pisa, Italy, Sergio Saponara University of Pisa, Italy
	10:20 10m Talk		Rigorous Design of FDIR Systems with BIP InterAVT Iulia Dragomir , Saddek Bensalem Verimag