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ICSE 2021
Mon 17 May - Sat 5 June 2021
Fri 28 May 2021 19:50 - 20:10 at Blended Sessions Room 3 - 4.5.3. Programming: Low Level Chair(s): Ignacio Panach
Sat 29 May 2021 07:50 - 08:10 at Blended Sessions Room 3 - 4.5.3. Programming: Low Level

Inline assembly is still a common practice in low- level C programming, typically for efficiency reasons or for accessing specific hardware resources. Such embedded assembly codes in the GNU syntax (supported by major compilers such as GCC, Clang and ICC) have an interface specifying how the assembly codes interact with the C environment. For simplicity reasons, the compiler treats GNU inline assembly codes as blackboxes and relies only on their interface to correctly glue them into the compiled C code. Therefore, the adequacy between the assembly chunk and its interface (named compliance) is of primary importance, as such compliance issues can lead to subtle and hard-to-find bugs. We propose RUSTINA, the first automated technique for formally checking inline assembly compliance, with the extra ability to propose (proven) patches and (optimization) refinements in certain cases. RUSTINA is based on an original formalization of the inline assembly compliance problem together with novel dedicated algorithms. Our prototype has been evaluated on 202 Debian packages with inline assembly (2640 chunks), finding 2036 issues in 77 packages – 849 significant issues in 44 packages (including major projects such as ffmpeg or ALSA), and proposing patches for 95% of them. Currently, 27 patches have already been accepted (solving 53 significant issues), with positive feedback from development teams.

Fri 28 May

Displayed time zone: Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna change

19:30 - 20:30
4.5.3. Programming: Low LevelTechnical Track / Journal-First Papers at Blended Sessions Room 3 +12h
Chair(s): Ignacio Panach Universidad de Valencia
19:30
20m
Paper
A Chaos Engineering System for Live Analysis and Falsification of Exception-handling in the JVMJournal-First
Journal-First Papers
Long Zhang KTH Royal Institute of Technology, Brice Morin SINTEF, Philipp Haller KTH, Benoit Baudry KTH Royal Institute of Technology, Martin Monperrus KTH Royal Institute of Technology
Link to publication DOI Pre-print Media Attached
19:50
20m
Paper
Interface Compliance of Inline Assembly: Automatically Check, Patch and RefineACM SIGSOFT Distinguished PaperArtifact ReusableTechnical TrackArtifact Available
Technical Track
Frédéric Recoules CEA, List, Sébastien Bardin CEA LIST, University Paris-Saclay, France, Richard Bonichon Tweag I/O, Paris, France, Matthieu Lemerre CEA LIST, University Paris-Saclay, France, Laurent Mounier Univ. Grenoble Alpes. VERIMAG, Grenoble, France, Marie-Laure Potet Univ. Grenoble Alpes. VERIMAG, Grenoble, France
Pre-print Media Attached
20:10
20m
Paper
Enabling Software Resilience in GPGPU Applications via Partial Thread ProtectionTechnical Track
Technical Track
Lishan Yang William & Mary, Bin Nie William & Mary, Adwait Jog William & Mary, Evgenia Smirni William & Mary
Pre-print Media Attached

Sat 29 May

Displayed time zone: Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna change

07:30 - 08:30
07:30
20m
Paper
A Chaos Engineering System for Live Analysis and Falsification of Exception-handling in the JVMJournal-First
Journal-First Papers
Long Zhang KTH Royal Institute of Technology, Brice Morin SINTEF, Philipp Haller KTH, Benoit Baudry KTH Royal Institute of Technology, Martin Monperrus KTH Royal Institute of Technology
Link to publication DOI Pre-print Media Attached
07:50
20m
Paper
Interface Compliance of Inline Assembly: Automatically Check, Patch and RefineACM SIGSOFT Distinguished PaperArtifact ReusableTechnical TrackArtifact Available
Technical Track
Frédéric Recoules CEA, List, Sébastien Bardin CEA LIST, University Paris-Saclay, France, Richard Bonichon Tweag I/O, Paris, France, Matthieu Lemerre CEA LIST, University Paris-Saclay, France, Laurent Mounier Univ. Grenoble Alpes. VERIMAG, Grenoble, France, Marie-Laure Potet Univ. Grenoble Alpes. VERIMAG, Grenoble, France
Pre-print Media Attached
08:10
20m
Paper
Enabling Software Resilience in GPGPU Applications via Partial Thread ProtectionTechnical Track
Technical Track
Lishan Yang William & Mary, Bin Nie William & Mary, Adwait Jog William & Mary, Evgenia Smirni William & Mary
Pre-print Media Attached