Automated Test Mapping and Coverage for Network Topologies
Communication devices such as routers and switches play a critical role in the reliable functioning of embedded system networks. Dozens of such devices may be part of an embedded system network, and they need to be tested in conjunction with various computational elements on actual hardware, in many different configurations that are representative of actual operating networks. An individual physical network topology can be used as the basis for a test system that can execute many test cases, by identifying the part of the physical network topology that corresponds to the configuration required by each individual test case. Given a set of available test systems and a large number of test cases, the problem is to determine for each test case, which of the test systems are suitable for executing the test case, and to provide the mapping that associates the test case elements (the logical network topology) with the appropriate elements of the test system (the physical network topology).
We studied a real industrial environment where this problem was originally handled by a simple software procedure that was very slow in many cases, and also failed to provide thorough coverage of each network’s elements. In this paper, we represent both the test systems and the test cases as graphs, and develop a new prototype algorithm that a) determines whether or not a test case can be mapped to a subgraph of the test system, b) rapidly finds mappings that do exist, and c) exercises diverse sets of network nodes when multiple mappings exist for the test case. The prototype has been implemented and applied to over 10,000 combinations of test cases and test systems, and reduced the computation time by a factor of more than 80 from the original procedure. In addition, relative to a meaningful measure of network topology coverage, the mappings achieved an increased level of thoroughness in exercising the elements of each test system.
Mon 16 JulDisplayed time zone: Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna change
14:00 - 15:30 | Testing and Fault LocalizationISSTA Technical Papers at Zurich II Chair(s): Cindy Rubio-González University of California, Davis | ||
14:00 20mTalk | Test Case Prioritization for Acceptance Testing of Cyber Physical Systems: A Multi-Objective Search-Based Approach ISSTA Technical Papers Seung Yeob Shin SnT Centre/University of Luxembourg, Shiva Nejati SnT Centre/University of Luxembourg, Mehrdad Sabetzadeh SnT Centre/University of Luxembourg, Lionel C. Briand SnT Centre/University of Luxembourg, Frank Zimmer SES Techcom | ||
14:20 20mTalk | Bench4BL: Reproducibility Study on the Performance of IR-Based Bug Localization ISSTA Technical Papers Jaekwon Lee University of Luxembourg, Luxembourg, Dongsun Kim University of Luxembourg, Tegawendé F. Bissyandé University of Luxembourg, Luxembourg, Woosung Jung Seoul National University of Education, Yves Le Traon University of Luxembourg | ||
14:40 20mTalk | Automated Test Mapping and Coverage for Network Topologies ISSTA Technical Papers Per Erik Strandberg Westermo Research and Development AB, Thomas Ostrand , Elaine Weyuker Mälardalen University, Daniel Sundmark Mälardalen University, Wasif Afzal Mälardalen University | ||
15:00 20mTalk | Evaluating Test-Suite Reduction in Real-World Software Evolution ISSTA Technical Papers August Shi University of Illinois at Urbana-Champaign, Alex Gyori Facebook, Muhammad Suleman Mahmood University of Illinois at Urbana-Champaign, Peiyuan Zhao University of Illinois at Urbana-Champaign, Darko Marinov University of Illinois at Urbana-Champaign | ||
15:20 10m | Q&A in groups ISSTA Technical Papers |