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ISSTA 2018
Sun 15 - Sat 21 July 2018 Amsterdam, Netherlands
co-located with ECOOP and ISSTA 2018
Mon 16 Jul 2018 14:40 - 15:00 at Zurich II - Testing and Fault Localization Chair(s): Cindy Rubio-González

Communication devices such as routers and switches play a critical role in the reliable functioning of embedded system networks. Dozens of such devices may be part of an embedded system network, and they need to be tested in conjunction with various computational elements on actual hardware, in many different configurations that are representative of actual operating networks. An individual physical network topology can be used as the basis for a test system that can execute many test cases, by identifying the part of the physical network topology that corresponds to the configuration required by each individual test case. Given a set of available test systems and a large number of test cases, the problem is to determine for each test case, which of the test systems are suitable for executing the test case, and to provide the mapping that associates the test case elements (the logical network topology) with the appropriate elements of the test system (the physical network topology).

We studied a real industrial environment where this problem was originally handled by a simple software procedure that was very slow in many cases, and also failed to provide thorough coverage of each network’s elements. In this paper, we represent both the test systems and the test cases as graphs, and develop a new prototype algorithm that a) determines whether or not a test case can be mapped to a subgraph of the test system, b) rapidly finds mappings that do exist, and c) exercises diverse sets of network nodes when multiple mappings exist for the test case. The prototype has been implemented and applied to over 10,000 combinations of test cases and test systems, and reduced the computation time by a factor of more than 80 from the original procedure. In addition, relative to a meaningful measure of network topology coverage, the mappings achieved an increased level of thoroughness in exercising the elements of each test system.

Mon 16 Jul
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14:00 - 15:30: ISSTA Technical Papers - Testing and Fault Localization at Zurich II
Chair(s): Cindy Rubio-GonzálezUniversity of California, Davis
issta-2018-Technical-Papers14:00 - 14:20
Seung Yeob ShinSnT Centre/University of Luxembourg, Shiva NejatiSnT Centre/University of Luxembourg, Mehrdad SabetzadehSnT Centre/University of Luxembourg, Lionel C. BriandSnT Centre/University of Luxembourg, Frank ZimmerSES Techcom
issta-2018-Technical-Papers14:20 - 14:40
Jaekwon LeeUniversity of Luxembourg, Luxembourg, Dongsun KimUniversity of Luxembourg, Tegawendé F. BissyandéUniversity of Luxembourg, Luxembourg, Woosung JungSeoul National University of Education, Yves Le TraonUniversity of Luxembourg
issta-2018-Technical-Papers14:40 - 15:00
Per Erik StrandbergWestermo Research and Development AB, Thomas Ostrand, Elaine WeyukerMälardalen University, Daniel SundmarkMälardalen University, Wasif AfzalMälardalen University
issta-2018-Technical-Papers15:00 - 15:20
August ShiUniversity of Illinois at Urbana-Champaign, Alex GyoriFacebook, Muhammad Suleman MahmoodUniversity of Illinois at Urbana-Champaign, Peiyuan ZhaoUniversity of Illinois at Urbana-Champaign, Darko MarinovUniversity of Illinois at Urbana-Champaign
issta-2018-Technical-Papers15:20 - 15:30