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ICSE 2021
Mon 17 May - Sat 5 June 2021
Fri 28 May 2021 19:30 - 19:50 at Blended Sessions Room 3 - 4.5.3. Programming: Low Level Chair(s): Ignacio Panach
Sat 29 May 2021 07:30 - 07:50 at Blended Sessions Room 3 - 4.5.3. Programming: Low Level

Software systems contain resilience code to handle those failures and unexpected events happening in production. It is essential for developers to understand and assess the resilience of their systems. Chaos engineering is a technology that aims at assessing resilience and uncovering weaknesses by actively injecting perturbations in production. In this paper, we propose a novel design and implementation of a chaos engineering system in Java called ChaosMachine. It provides a unique and actionable analysis on exception-handling capabilities in production, at the level of try-catch blocks. To evaluate our approach, we have deployed ChaosMachine on top of 3 large-scale and well-known Java applications totaling 630k lines of code. Our results show that ChaosMachine reveals both strengths and weaknesses of the resilience code of a software system at the level of exception handling.

Conference Day
Fri 28 May

Displayed time zone: Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna change

19:30 - 20:30
4.5.3. Programming: Low LevelTechnical Track / Journal-First Papers at Blended Sessions Room 3 +12h
Chair(s): Ignacio PanachUniversidad de Valencia
19:30
20m
Paper
A Chaos Engineering System for Live Analysis and Falsification of Exception-handling in the JVMJournal-First
Journal-First Papers
Long ZhangKTH Royal Institute of Technology, Brice MorinSINTEF, Philipp HallerKTH, Benoit BaudryKTH Royal Institute of Technology, Martin MonperrusKTH Royal Institute of Technology
Link to publication DOI Pre-print Media Attached
19:50
20m
Paper
Interface Compliance of Inline Assembly: Automatically Check, Patch and RefineACM SIGSOFT Distinguished PaperArtifact ReusableTechnical TrackArtifact Available
Technical Track
Frédéric RecoulesCEA, List, Sébastien BardinCEA LIST, University Paris-Saclay, France, Richard BonichonTweag I/O, Paris, France, Matthieu LemerreCEA LIST, University Paris-Saclay, France, Laurent MounierUniv. Grenoble Alpes. VERIMAG, Grenoble, France, Marie-Laure PotetUniv. Grenoble Alpes. VERIMAG, Grenoble, France
Pre-print Media Attached
20:10
20m
Paper
Enabling Software Resilience in GPGPU Applications via Partial Thread ProtectionTechnical Track
Technical Track
Lishan YangWilliam & Mary, Bin NieWilliam & Mary, Adwait JogWilliam & Mary, Evgenia SmirniWilliam & Mary
Pre-print

Conference Day
Sat 29 May

Displayed time zone: Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna change

07:30 - 08:30
07:30
20m
Paper
A Chaos Engineering System for Live Analysis and Falsification of Exception-handling in the JVMJournal-First
Journal-First Papers
Long ZhangKTH Royal Institute of Technology, Brice MorinSINTEF, Philipp HallerKTH, Benoit BaudryKTH Royal Institute of Technology, Martin MonperrusKTH Royal Institute of Technology
Link to publication DOI Pre-print Media Attached
07:50
20m
Paper
Interface Compliance of Inline Assembly: Automatically Check, Patch and RefineACM SIGSOFT Distinguished PaperArtifact ReusableTechnical TrackArtifact Available
Technical Track
Frédéric RecoulesCEA, List, Sébastien BardinCEA LIST, University Paris-Saclay, France, Richard BonichonTweag I/O, Paris, France, Matthieu LemerreCEA LIST, University Paris-Saclay, France, Laurent MounierUniv. Grenoble Alpes. VERIMAG, Grenoble, France, Marie-Laure PotetUniv. Grenoble Alpes. VERIMAG, Grenoble, France
Pre-print Media Attached
08:10
20m
Paper
Enabling Software Resilience in GPGPU Applications via Partial Thread ProtectionTechnical Track
Technical Track
Lishan YangWilliam & Mary, Bin NieWilliam & Mary, Adwait JogWilliam & Mary, Evgenia SmirniWilliam & Mary
Pre-print