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ICSE 2022
Sun 8 - Fri 27 May 2022
Tue 10 May 2022 05:25 - 05:30 at ICSE room 4-odd hours - Validation and Verification 1 Chair(s): Grischa Liebel
Wed 11 May 2022 13:05 - 13:10 at ICSE room 4-odd hours - Synthesis and Reverse Engineering Chair(s): Reed Milewicz

Reactive synthesis is an automated procedure to obtain a correct-by-construction reactive system from its temporal logic specification. GR(1) is an expressive fragment of LTL that enables efficient synthesis and has been recently used in different contexts and application domains.

In this paper we investigate the dynamic-update problem for GR(1): updating the behavior of an already running synthesized controller such that it would safely and dynamically, without stopping, start conforming to a modified, up-to-date specification. We formally define the dynamic-update problem and present a sound and complete solution that is based on the computation of a bridge-controller.

We implemented the work in the Spectra synthesis and execution environment and evaluated it over benchmark specifications. The evaluation shows the efficiency and effectiveness of using dynamic updates. The work advances the state-of-the-art in reactive synthesis and opens the way to its use in application domains where dynamic updates are a necessary requirement.

Tue 10 May

Displayed time zone: Eastern Time (US & Canada) change

05:00 - 06:00
Validation and Verification 1SEIP - Software Engineering in Practice / Technical Track at ICSE room 4-odd hours
Chair(s): Grischa Liebel Reykjavik University
05:00
5m
Talk
Unreliable Test Infrastructures in Automotive Testing Setups
SEIP - Software Engineering in Practice
Claudius Jordan Technical University of Munich, Philipp Foth Technical University of Munich, Alexander Pretschner TU Munich, Matthias Fruth TraceTronic GmbH
Pre-print Media Attached
05:05
5m
Talk
How Does Code Reviewing Feedback Evolve? A Longitudinal Study at Dell EMC
SEIP - Software Engineering in Practice
Ruiyin Wen McGill University, Maxime Lamothe Polytechnique Montréal, Shane McIntosh University of Waterloo
Pre-print Media Attached
05:10
5m
Talk
Linear-time Temporal Logic guided Greybox Fuzzing
Technical Track
Ruijie Meng National University of Singapore, Singapore, Zhen Dong Fudan University, China, Jialin Li National University of Singapore, Singapore, Ivan Beschastnikh University of British Columbia, Abhik Roychoudhury National University of Singapore
DOI Pre-print Media Attached
05:15
5m
Talk
ExAIS: Executable AI Semantics
Technical Track
Richard Schumi Singapore Management University, Jun Sun Singapore Management University
Pre-print Media Attached
05:20
5m
Talk
Nalin: Learning from Runtime Behavior to Find Name-Value Inconsistencies
Technical Track
Jibesh Patra University of Stuttgart, Michael Pradel University of Stuttgart
Pre-print Media Attached
05:25
5m
Talk
Dynamic Update for Synthesized GR(1) Controllers
Technical Track
Gal Amram Tel Aviv University, Shahar Maoz Tel Aviv University, Israel, Itai Segall Nokia Bell-Labs, Matan Yossef Tel Aviv University
Pre-print Media Attached

Wed 11 May

Displayed time zone: Eastern Time (US & Canada) change

13:00 - 14:00
Synthesis and Reverse EngineeringTechnical Track / Journal-First Papers at ICSE room 4-odd hours
Chair(s): Reed Milewicz Sandia National Laboratories
13:00
5m
Talk
Learning to Find Usages of Library Functions in Optimized Binaries
Journal-First Papers
Toufique Ahmed University of California at Davis, Prem Devanbu Department of Computer Science, University of California, Davis, Anand Ashok Sawant University of California, Davis
Link to publication DOI Pre-print Media Attached
13:05
5m
Talk
Dynamic Update for Synthesized GR(1) Controllers
Technical Track
Gal Amram Tel Aviv University, Shahar Maoz Tel Aviv University, Israel, Itai Segall Nokia Bell-Labs, Matan Yossef Tel Aviv University
Pre-print Media Attached
13:10
5m
Talk
Push-Button Synthesis of Watch Companions for Android Apps
Technical Track
Cong Li Nanjing University, Yanyan Jiang Nanjing University, Chang Xu Nanjing University
Link to publication DOI Pre-print Media Attached
13:15
5m
Talk
Jigsaw: Large Language Models meet Program Synthesis
Technical Track
Naman Jain Microsoft Research, Skanda Vaidyanath Stanford, Arun Iyer Microsoft Research, India, Nagarajan Natarajan Microsoft Research, India, Suresh Parthasarathy Microsoft Research, India, Sriram Rajamani Microsoft Research, Rahul Sharma Microsoft Research
Pre-print Media Attached
13:20
5m
Talk
SapientML: Synthesizing Machine Learning Pipelines by Learning from Human-Written Solutions
Technical Track
Ripon Saha , Akira Ura Fujitsu Ltd., Sonal Mahajan Uber Technologies Inc., Chenguang Zhu University of Texas at Austin, Linyi Li University of Illinois at Urbana-Champaign, Yang Hu The University of Texas at Austin, Hiroaki Yoshida AMD, Sarfraz Khurshid The University of Texas at Austin, Mukul Prasad Fujitsu Research of America
Pre-print Media Attached
13:25
5m
Talk
Static Stack-Preserving Intra-Procedural Slicing of WebAssembly BinariesBest Artifact Award
Technical Track
Quentin Stiévenart Vrije Universiteit Brussel, David Binkley Loyola University Maryland, Coen De Roover Vrije Universiteit Brussel
DOI Pre-print Media Attached

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